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CXA7002R
I2C Bus Compatible Audio Video (AV) Switch & Electronic Volume Control
Description The Sony CXA7002R is an Audio/Video switch designed primarily for application in Digital Set Top Boxes. It provides video and audio routing from the digital encoder source to the TV and VCR scart (peri-television) connectors. In addition, the TV audio output has a programmable volume control. The chip is programmed by means of an I2C interface and can operate from a single or dual power supply. Target specifications: Canal+, BSkyB, TPS, NorDig, and ECCA Euro-Box Features Supply * Single: 0V, +5V, +12V * Dual: 0V, -5V, +5V and +12V (Low number of external parts required) Video * 2 scart switching (VCR, TV) * VCR input supports RGB mode * Integrated 75 drivers for direct video connection * Y/C mixer with trap for RF modulators * Switchable clamps on inputs * Low pass filters on six inputs * Controllable gain on encoder inputs * Adjustable gain on RGB outputs * Video output shutdown for low power modes * Fast blanking switch * Slow blanking switch for TV and VCR output * SVHS switch on VCR output * Y/C auxiliary input Audio * Four stereo audio inputs * Volume control (-56dB to +6dB in 2dB steps) * Additional +6dB gain on audio DAC inputs * Audio overlay facility * Volume bypass for TV and Phono outputs * Mono switching on TV, VCR outputs * Switchable audio limiter function * Switchable Mono output for RF modulators * Audio output disable for standby mode 64 pin LQFP (Plastic)
I2C and Logic * Fast mode compatible I2C bus * Function monitor with loop through * Interrupt output for function monitor and sync detect * Logic output pin * Sync detector for Y/CVBS inputs Applications * Digital Set Top Box * Integrated digital television Structure Bipolar silicon monolithic IC Absolute Maximum Ratings (Ta = 25C) unless stated 14 V * Supply voltage VCC * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 1.1 W (when mounted on the board) Operating Conditions * Single supply
12 0.6 V 5 0.25 V * Dual supply -5 0.25 V 5 0.25 V 12 0.6 V * Operating temperature Topr -20 to +75 C * Maximum ESD voltage 2 kV (Human Body Model)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E02750A41
CXA7002R
Block Diagram (1) Video Section
GAIN ADJUST DC Restore DC Restore DC Restore DC Restore DC Restore/ C Bias DC Restore /C Bias C Bias 63 VOUT_3 RED/CHROMA 1 VOUT_2 GREEN TV RGB Gain Control (+1, 2, 3dB) 2 VOUT_1 BLUE
DIG BLUE
VIN_1
6
VCR BLUE DIG GREEN/CVBS
VIN_2 54 VIN_3 7
VCR GREEN
VIN_4 53
DIG RED/CHROMA
VIN_5
8
VCR RED/CHROMA DIG CHROMA
VIN_7 51 VIN_6 9
AUX CHROMA VIN_13 55
C Bias 4 Sync Tip Clamp Sync Tip Clamp Sync Tip Clamp Sync Tip Clamp Sync Tip Clamp Mix Switch Mix Switch TRAP
DIG CVBS/LUMA
VIN_8 10
3
VOUT_7
RF MOD
DIG CVBS/LUMA
VIN_9 11
VCR CVBS/LUMA VIN_10 52
62 VOUT_4
LUMA/CVBS
TV
TV CVBS VIN_11 57
AUX Y/CVBS VIN_12 56
60 VOUT_5
CHROMA
Sync Detector VID_BIAS 5 GND 12 GND 37 -5V_GNDA 13 -5V_GNDA 36 -5V_GNDA 27 +12V 17 +5V_DIG 24 GND_DIG 25 AUD_BIAS 26 +5/12V_VCCA 28
INTERUPT
Bi-directional Control
VCR
61 VOUT_6
LUMA/CVBS
59 GND_VID 64 +5V_VOUT 58 +5V_VID 46 AUD_BIAS 35 VCC_AUD
Note) All video outputs contain 75 drivers.
-2-
(2) Audio Section
Mono Switch
12dB
31 MONO
Vol Bypass (Phono)
12dB
30 PHONO_R
Overlay on/off AUDIO SWITCH1 (TV) RIN_1 (DIG) RIN_2 (VCR) RIN_3 (TV/OVERLAY) RIN_4 (AUX) 41 44 47 49 -6dB -12dB -12dB -12dB Overlay on/off 2dB
Volume Control +6 to -56dB Limiter 2.2Vrms
Vol Bypass (TV)
12dB
16 RTV
TV ZCD Limiter 2.2Vrms 2dB Vol Bypass (TV) Mono Switch
LIN_1 (DIG) LIN_2 (VCR) LIN_3 (TV/OVERLAY) LIN_4 (AUX)
42 45 47 50
-6dB -12dB -12dB -12dB
12dB
15 LTV
-3-
Vol Bypass (Phono) Tone mix AUDIO SWITCH2 (VCR) Mono and R/L Switch Bias Mute H/W MUTE 19 Hardware Mute
12dB
29 PHONO_L
12dB
33 ROUT1
VCR
12dB
32 LOUT1
CXA7002R
CXA7002R
(3) Digital Section
FBLK_SW +3.5V 0V FBLK_IN1 20 FBLK_IN2 23 Logic Control 0/6/12V 21 TV_FBLK
14 LOGIC
SDA 38 SCL 39
18 FNC_TV
FNC_VCR 22
0/6/12V Sync Detector Monitor Interrupt Control 40 INTERUPT
-4-
CXA7002R
Pin Configuration
-5V_GNDA
INTERUPT
AUD_BIAS
GND_AUD
SYNC_ID
Vcc_AUD
48 RIN_4 49 LIN_4 50 VIN_7 51 VIN_10 52 VIN_4 53 VIN_2 54 VIN_13 55 VIN_12 56 VIN_11 57 +5V_VID 58 GND_VID 59 VOUT_5 60 VOUT_6 61 VOUT_4 62 VOUT_3 63 +5V_VOUT 64
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33 32 LOUT1 31 MONO 30 PHONO_R 29 PHONO_L 28 +5/+12V_VccA 27 -5V_GNDA 26 AUD_BIAS 25 GND_DIG 24 +5V_DIG 23 FBLK_IN2 22 FNC_VCR 21 TV_FBLK 20 FBLK_IN1 19 HW_MUTE 18 FNC_TV 17 +12V
1
VOUT_2
2
VOUT_1
3
VOUT_7
4
TRAP
5
VID_BIAS
6
VIN_1
7
VIN_3
8
VIN_5
9
VIN_6
10
VIN_8
11
VIN_9
12
GND
13
-5V_GNDA
14
LOGIC
15
LTV
16
RTV
-5-
ROUT1
RIN_3
RIN_2
RIN_1
LIN_3
LIN_2
LIN_1
GND
SDA
SCL
CXA7002R
Pin Description Pin No. Symbol Pin voltage [V] Equivalent circuit
VCC 6
Description
6 54 53
VIN_1 VIN_2 VIN_4
1.2k
2.5
54 53 2k
RGB signal inputs
VCC
2.5
1.2k
7
VIN_3 2.4
7
RGB signal input or CVBS signal input
3k
VCC
2.5 8 51 VIN_5 VIN_7 3.1
8 51
50k 1.2k
RGB signal inputs or Chrominance signal inputs
VCC
9 55
VIN_6 VIN_13
3.1
50k 9 55
Chrominance signal inputs
VCC
10 11 52 57 56
VIN_8 VIN_9 VIN_10 VIN_11 VIN_12
2.4
1.2k 10 57 11 56 52
CVBS/Luminance signal inputs
-6-
CXA7002R
Pin No. 2 1 63 62 61 3
Symbol VOUT_1 VOUT_2 VOUT_3 VOUT_4 VOUT_6 VOUT_7
Pin voltage [V]
Equivalent circuit
VCC 2 62
Description
0.6
20k
1 61 63 3
RGB/CVBS signal outputs
VCC
60
VOUT_5
1.8
20k
60
Chrominance signal output
VCC
VCC 40.8k
5
VID_BIAS
0.9
5 9.2k
Internal reference bias for video circuits. A capacitor is connected from this pin to GND. Typically 100nF
VCC
4
TRAP
2.4
1.2k 4 1.2k
Connects trap circuit for subcarrier
VCC 200
43
SYNC_ID
2.5
43 200
Sync detect circuit time constant, resistor and capacitor connection pin
VCC VCC/2
42 41
LIN_1 RIN_1
2.5
42 41
50k 50k
Audio signal inputs
VCC
VCC
45 44 48 47 50 49
LIN_2 RIN_2 LIN_3 RIN_3 LIN_4 RIN_4
45 44
2.5
6.25k 50k
48 47 50 49
Audio signal inputs
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CXA7002R
Pin No. 15 16 32 33 29 30 31
Symbol LTV RTV LOUT1 ROUT1 PHONO_L PHONO_R MONO
Pin voltage [V] 6.0 (Single)
Equivalent circuit
VCC 15 16 32 33
Description
40k
Audio signal outputs
0.0 (Dual)
VCC
29 30 31
VCC 25k
46
AUD_BIAS
2.5V (Single/ Dual)
46 25k
Capacitor Internal reference bias connected to GND. for audio circuit (Typically 22F)
6.0 (Single) 26 AUD_BIAS 0.0 (Dual)
26
VCC
VCC 40k 124 40k
Internal reference bias for audio circuit Connected directly to GND.
Capacitor connected to GND. (Typically 22F)
VCC
20 23
FBLK_IN1 FBLK_IN2
--
124 20 23
Fast blanking signal inputs
VCC
21
TV_FBLK
--
21
Fast blanking signal output
124 22 76.7k
22
FNC_VCR
--
16.5k
SCART function pin 8 input/output to VCR
124
18
FNC_TV
--
18 19k 36k
SCART function pin 8 output to TV
-8-
CXA7002R
Pin No.
Symbol
Pin voltage [V]
Equivalent circuit
Description
124
19
HW_MUTE
--
19
Mutes audio outputs when pin voltage is below 2V. This pin is normally connected to +5V.
14
LOGIC (Vcc = +12V) INTERUPT (Vcc = +5V)
VCC
--
14
40
--
40
Open connector logic outputs Typically connect to +5V through 10k resistor.
39
SCL
39
8k
I2C bus clock line
-- 38 24 64 58 35 17 13 17 36 28 12 37 25 34 59 SDA +5V_DIG +5V_VOUT +5V_VID Vcc_AUD +12V -5V_GNDA +5V/12V_VccA GND GND_DIG GND_AUD GND_VID 12.0 -5.0 (Dual) 0.0 (Single) 5.0 (Dual) 12.0 (Single) 0.0 0.0 0.0 0.0 5.0
38
I2C bus data line Digital supply Video output supply Video supply Audio supply Digital supply Audio supply/ground Audio supply
Digital ground Audio Ground Video ground
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CXA7002R
Electrical Characteristics Nominal conditions (Ta = 25C) Item Current consumption (Single ended supply) Current consumption (Dual supply) Symbol Icc1 Icc2 Icc3 Icc4 Icc5 Conditions +12 supply, no signal, no load +5 supply, no signal, no load +12 supply, no signal, no load +5 supply, no signal, no load -5 supply, no signal, no load Min. -- -- -- -- -50 Typ. 30 60 10 80 -20 Max. 55 85 30 110 -- Unit mA mA mA mA mA
(1) Video System Nominal conditions single supply (Ta = 25C, +5V/12V_VccA = +12V, -5V_GNDA = 0V, +5V_VID = +5V, +5V_VOUT = +5V, +5V_DIG = +5V) Item Sync tip clamp voltage at input Symbol Vclmp1 Cbias1 Cbias2 RGB dc restore input voltage Sync tip clamp voltage at output Chroma bias output voltage RGB dc restore output voltage Gain (Vout1 to 7) RGB1 Vclmp2 Cbias3 RGB2 GVv Conditions Vin3, Vin8, Vin9, Vin10, Vin11, Vin12 inputs. (Vin3 set to CVBS mode) (Fig. 1) Vin5, Vin7 inputs. Clamps set to Chroma bias mode. (Fig. 1) Vin6, Vin13 inputs. (Fig. 1) Vin1, Vin2, Vin3, Vin4, Vin5, Vin7 inputs. (Vin3 & Vin5 set to RGB mode) (Fig. 1) Vout4, Vout6 outputs (Fig. 1) Vout3, Vout5 outputs (Fig. 1) Vout1, Vout2, Vout3 outputs (Fig. 1) f = 200kHz, 0.3Vp-p input, RGB Gain = 0dB, Input Gain = 0dB (Fig. 2) f = 200kHz, 0.3Vp-p input, RGB Gain = +1dB, Input Gain = 0dB (Fig. 2) f = 200kHz, 0.3Vp-p input, RGB Gain = +2dB, Input Gain = 0dB (Fig. 2) f = 200kHz, 0.3Vp-p input, RGB Gain = +3dB, Input Gain = 0dB (Fig. 2) f = 200kHz, 0.3Vp-p input, Video gain = +1dB (Fig. 2) f = 200kHz, 0.3Vp-p input, Video gain = +3dB (Fig. 2) f = 200kHz, 0.3Vp-p input, Video gain = +6dB (Fig. 2) Min. -- -- -- -- -- -- -- 5.5 Typ. 2.4 3.1 2.45 2.5 0.3 1.8 0.6 6.0 Max. -- -- -- -- -- -- -- 6.5 Unit V V V V V V V dB
Chroma bias input voltage
GVRGB1
6.5
7.0
7.5
dB
Gain (Vout1, 2, 3)
GVRGB2
7.5
8.0
8.5
dB
GVRGB3 Gi/p1 Video input gain Vin 1, 3, 5, 6, 8, 9 Gi/p1 Gi/p1
8.5 6.5 8.5 11.5
9.0 7.0 9.0 12.0
9.5 7.5 9.5 12.5
dB dB dB dB
- 10 -
CXA7002R
Item
Symbol
Conditions 0.3Vp-p input, frequency where output level is -3dB with 200kHz serving as 0dB. Filter Bypassed. (Fig. 2) 0.3Vp-p input, frequency where output level is -3dB with 200kHz serving as 0dB. (Fig. 2) 200kHz input applied to any video (Fig. 2) 200kHz input applied to any video (Fig. 2) f = 4.43MHz, 1Vp-p input (Fig. 2) Falling edge delay from RGB to fast blank signal. Measured at 20% level. (Fig. 2) 2V applied to Vout5 with series 75 resistor. Measured voltage at pin and calculate Zout. (Fig. 2) Ratio of 0.7Vp-p white video signal to "black line" noise. Weighted using CCIR 567. HPF@5kHz, LPF@5MHz. (Fig. 2)
Input pin V plus V2
Min.
Typ.
Max.
Unit
Bandwidth (Vout1 to 6)
fV3dB
15
30
--
MHz
Bandwidth (Vout7) Mixer on - No trap components Input dynamic range Output dynamic range Cross talk Fast blanking to RGB delay Vout5 impedance when switched to ground
fV3dB VDRVI VDRVO Vctv DelFB
8 1.4 2.8 --
30 -- -- -65
-- -- -- -- 50
MHz Vp-p Vp-p dB ns
ZVout5
--
1
--
S/N ratio
S/NV
--
74
--
dB
Non-linearity
Lin
V1 = Pin voltage + 0.5V, V2 = Pin voltage + 1V At output, non-linearity V2 = -1 x 100 (Fig. 2) V1 x 2 1.7Vp-p 5-step modulated staircase. (Chroma & Burst are 150mVp-p, 4.43MHz) (Fig. 2) As above. (Fig. 2) Measured 27MHz signal relative to signal at 1MHz. (Fig. 2)
V1
-4
0
4
%
Differential gain Differential phase Filter specification Attenuation @27MHz
DG DP
-3 -3
0 0
3 3
% deg
Attn
--
-47
-24
dB
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CXA7002R
Audio System Unless otherwise stated: input coupling capacitor 1F; output coupling capacitor of 10F; load of 10k. Nominal conditions single supply (Ta = 25C, +5V/12V_VCCA = +12V, -5V_GNDA = 0V, +5V_VID = +5V, +5V_VOUT = +5V, +5V_DIG = +5V, GND_VID = 0V) Nominal conditions dual supply (Ta = 25C, +5V/12V_VCCA = +5V, -5V_GNDA = -5V, +5V_VID = +5V, +5V_VOUT = +5V, +5V_DIG = +5V, GND_VID = 0V) Item Input pin voltage (Single/Dual supply) Output pin voltage (Single supply) Output pin voltage (Dual supply) Output pin voltage when disabled (Single/Dual supply) Gain Input Rin1 or Lin1 Rin1 or Lin1 Rin1 + Lin1 Output TV or Phono VCR TV (mono mix) GVA1 GVA2 GVA3 f = 10kHz, 0.3Vp-p input (Fig. 4) f = 10kHz, 0.3Vp-p input (Fig. 4) f = 10kHz, 0.3Vp-p stereo input, TV volume set to 0dB, TV mono switch on (Fig. 4) f = 10kHz, 0.3Vp-p stereo input, TV volume set to 0dB (Note 1) (Fig. 4) f = 10kHz, 0.3Vp-p input, TV volume set to 0dB (Fig. 4) f = 10kHz, 0.3Vp-p stereo input, VCR mono switch on (Fig. 4) f = 10kHz, 0.3Vp-p stereo input, TV volume set to 0dB (Note 1) (Fig. 4) f = 10kHz, 0.3Vp-p input, VCR mono switch on (Fig. 4) 5.7 5.7 5.7 6.2 6.2 6.2 6.7 6.7 6.7 dB dB dB Symbol VAPIN1 VAPIN2 VAPIN2 VAPIN3 Conditions No signal, no load (Fig. 3) No signal, no load (Fig. 3) No signal, no load (Fig. 3) No signal, no load (Fig. 3) Min. 2.25 5.75 -0.25 -0.25 Typ. 2.5 6 0 0 Max. 2.75 6.25 0.25 0.25 Unit V V V V
Rin1 + Lin1 Rin2, 3, 4 or Lin2, 3, 4 Rin1 + Lin1 Rin2 + Lin2 Rin3 + Lin3 Rin4 + Lin4 Rin2 + Lin2 Rin3 + Lin3 Rin4 + Lin4 Rin3 Lin3
MONO TV, VCR, Phono VCR (mono mix) MONO VCR (mono mix) RTV, ROUT1, Phono_R LTV, LOUT1, Phono_L
GVA4 GVA5 GVA6 GVA7
5.7 -0.3 5.7 -0.3
6.2 0.2 6.2 0.2
6.7 0.7 6.7 0.7
dB dB dB dB
GVA9
-0.3
0.2
0.7
dB
GVA10 GVA11
f = 10kHz, 0.3Vp-p, Lin3 has no signal Audio overlay enabled. -12.5 -11.75 -11.25 (Fig. 4) f = 10kHz, 0.3Vp-p input Audio overlay enabled. (Fig. 4) -12.5 -11.75 -11.25
dB dB
Note 1) Mono switch set to mix RTV & LTV after volume control.
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CXA7002R
Item Audio frequency response
Symbol FAF
Condition 0.3Vp-p input. Output/Input gain at 30kHz with 10kHz serving as 0dB (Fig. 4) f = 1kHz, 0.5Vrms, unweighted response; LPF @400Hz, HPF @80kHz (Fig. 4) f = 1kHz, RIN1/LIN1 input amplifier set to -6dB. Dual supply mode used. (Fig. 4) f = 1kHz (Fig. 4) f = 10kHz, 1Vrms input on one input, measure on any audio output (Fig. 4) (Excluding any external series resistor) (Fig. 4) f = 1kHz, 1Vrms input (0dB volume). (20Hz to 20kHz) BPF + A weighting filter (Fig. 4) f = 10Hz, 0.5Vp-p. Set by I2C (Fig. 4) f = 1kHz, 2.5Vrms input. Measure TV pk-pk output with limiter switched on. (Fig. 4) f = 1kHz, 1Vrms input (Fig. 4)
Min. -0.3
Typ. 0
Max. 0.3
Unit dB
Distortion Input dynamic range Rin2, 3, 4/Lin2, 3, 4 Input dynamic range Rin1/Lin1 Cross talk (Channel separation) Input impedance Rin1, 2, 3, 4/Lin1, 2, 3, 4 S/N ratio Electronic Volume Control Volume attenuation step Audio limiter level Mute TV I/P Mute or VCR I/P MUTE
THD
--
0.005
0.1
%
VdA1 VdA1 VctA Zin1 S/NA
2.5 1.25 -- -- 80
2.9 1.45 -90 100 --
-- -- -- -- --
Vrms Vrms dB dB dB
AEVC Alimit
1.6 --
2 2.2
2.4 --
dB Vrms
Amute
--
-85
--
dB
- 13 -
CXA7002R
Digital Characteristics (1) I2C Interface The I2C interface is compliant with Philips I2C Fast Mode specification (data April 1995). The interface is also capable of interfacing to +3.3V or +5V logic levels. Item High level input voltage Low level input voltage Low level output voltage Hysteresis of schmitt trigger input Spike suppression Fall time for SDA line SCL clock frequency Bus free time between a stop and start Hold time (repeated start condition) Low period of SCL clock High period of SCL clock Setup time for a repeated start condition Data hold time Data setup time Setup time for stop condition Symbol VIH VIL VOL VHYST With SDA, 3mA current supplied With SDA, 6mA current supplied VIH - VIL 400pF bus load I2C bus line requirement I2C bus line requirement I2C bus line requirement I 2C bus line requirement I2C bus line requirement I2C bus line requirement I2C bus line requirement I 2C I 2C bus line requirement bus line requirement Condition Min. 2.3 0 0 0 -- -- -- 0 1.3 0.6 1.3 0.6 0.6 0 100 0.6 Typ. -- -- -- -- 0.5 -- -- -- -- -- -- -- -- -- -- -- Max. 5.5 1.5 0.4 0.6 -- 50 300 400 -- -- -- -- -- 0.9 -- -- Unit V V V V ns ns kHz s s s s s s s s
tSP tF tSCL tBUF tHD;STA tLOW tHIGH tSU;SDA tHD;DAT tSU;DAT tSU;STO
tBUF
tR
tF
tHD;STA
tHD;STA P S tLOW tSU;DAT tHIGH tSU;DAT
tSU;STA
tSU;STO Sr P
- 14 -
CXA7002R
(2) Slow Blanking Load = 10k, supply +12V = +12V Item Input threshold low level Input threshold high level Output low level (Int TV mode) Output level (Ext 16:9 mode) Output level (Ext 4:3 mode) Symbol VTH1 VTH2 VOUT1 VOUT2 VOUT3 Load = 10k Load = 10k Load = 10k Condition Min. -- -- -- 4.8 10 Typ. 3 8.1 0.3 5.5 11 Max. -- -- 0.8 6.5 -- Unit V V V V V
(3) Fast Blanking Output load = 150, supply +5V_VOUT = +5V Item Input threshold Input current Output low level Output high level Symbol VTH3 IIN1 VOUT4 VOUT5 Condition Measured on fast blanking input 1, 2 +2V applied to input Load = 150 Load = 150 3 -- Min. -- -- Typ. 0.7 2 Max. -- -- 0.2 -- Unit V A V V
(4) logic and interrupt output These outputs are open collector type and normally connected to +5V through a 10k resistor. Item Output low voltage Symbol DIGVOUTL IOL = 1mA Condition Min. -- Typ. -- Max. 0.4 Unit V
- 15 -
CXA7002R
+5V 68k 22F 100nF I2C SCL SDA
+5V
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 75 75 75 75 75 75 75 100nF 100nF 100nF 100nF 100nF 100nF 100nF +5V 51 52 53 54 55 56 57 58 59 60 61 62 63 +5V Measurement Point 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 +12V +5V 22F +12V
V
100nF
V
100nF 100nF 100nF 100nF 100nF
Measurement Point
75
75
75
75
75
Fig. 1. Video System (DC Tests) DC measured from Pins 1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 51, 52, 53, 54, 55, 56, 57, 60, 61, 62, 63 Notes) 1. All supplies de-coupled close to the supply pins, 17, 24, 28, 58, 64 with 10nF and 10F capacitors. 2. All video outputs are unloaded during tests.
- 16 -
75
100nF
V
Measurement Point
CXA7002R
+5V 68k 100nF 22F 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 75 75 75 75 75 75 75 100nF 100nF 100nF 100nF 100nF 100nF 100nF +5V 51 52 53 54 55 56 57 58 59 60 61 62 63 +5V Input Signal 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 +12V +5V 22F +12V I2C SCL SDA
+5V
100nF
100nF
100nF
100nF
100nF
100nF
100nF
V
150 150 150 150 150 150 150
Input Signal
Measurement Point
75
75
75
75
75
Fig. 2. Video System (Gain, Dynamic Range, Bandwidth, Differential Gain, Differential Phase, Crosstalk, Linearity) Signal applied to Pins 51, 52, 53, 54, 55, 56, 57, 6, 7, 8, 9, 10, 11 Output signal measured from Pins 60, 61, 62, 63, 64, 1, 2, 3 Notes) 1. All supplies de-coupled close to the supply pins, 17, 24, 28, 58, 64 with 10nF and 10F capacitors. 2. For video crosstalk tests all video inputs are terminated with 37.5.
- 17 -
75
CXA7002R
-5V I2C SCL SDA
V
Input Measurement Point
22F
+5V
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 51 52 53 54 55 56 57 +5V 58 59 60 61 62 63 +5V 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 +12V +5V +12V +5V Output Measurement Point
V
-5V
22F
100nF
-5V
Fig. 3. Audio System (DC Tests) DC measured from Pins 29, 30, 31, 32, 41, 42, 44, 45, 47, 48, 49, 50 Notes) 1. Single audio supply configuration shown. Operate switches for dual supply configuration. 2. All supplies de-coupled close to the supply pins, 17, 24, 28, 58, 64 with 10nF and 10F capacitors.
- 18 -
CXA7002R
1F
1F
1F
1F
1F
1F
1F
1F
-5V I2 C SCL SDA Input Signal 10F
22F
+5V
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 51 52 53 54 55 56 57 +5V 58 59 60 61 62 63 +5V 64 1 2 3 4 5
100nF
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 6 7 8 9 10 11 12 13 14 15 16
10F 10F 10F 10F +12V +5V
-5V
V
10k
Output Measurement Point
22F
+5V
+12V
10F 10F
-5V
Fig. 4. Audio System (Gain, Bandwidth, Signal to Noise, Electronic Volume, Zero Cross Detection, Dynamic Range, Crosstalk) Signal applied to Pins 41, 42, 44, 45, 47, 48, 49, 50 Output signal measured from Pins 29, 30, 31, 32, 33 Notes) 1. Single audio supply configuration shown. Operate switches for dual supply configuration. 2. All supplies de-coupled close to the supply pins, 17, 24, 58, 64 with 10nF and 10F capacitors.
- 19 -
CXA7002R
I2C Control Data Format S Slave address A S: Start condition Address = 90H I2C Data Structure (write mode) b7 Address Data1 Data2 Data3 Data4 Data5 Data6 Data7 1 b6 0 b5 0 b4 1 b3 0 VOLUME CONTROL TV VOL BYPASS ZCD VCR AUDIO SELECT AUDIO DISABLE LOGIC LEVEL FNC TV RGB GAIN VIN5 CLAMP ENABLE VOUT5 VIN7 CLAMP ENABLE VOUT4 VIN3 CLAMP ENABLE VOUT3 TV AUDIO SELECT 0 b2 0 b1 0 b0 0 = Write TV AUD MUTE PHONO BYPASS DATA1 A DATA2 A DATA3 A DATA4 A DATAn AP
A: Acknowledge
P: Stop condition
AUDIO VCR MONO LIMITER SWITCH MONO SWITCH TV AUD MUTE TV MONO SWITCH TV INPUT MUTE
VCR INPUT OVERLAY MUTE ENABLE FAST BLANK TV VIDEO SWITCH MIXER CONTROL ENABLE VOUT2 ENABLE VOUT1
VIDEO INPUT GAIN VCR VIDEO SWITCH FILTER CONTROL VOUT5_0 V SYNC SEL ENABLE VOUT7
FNC VCR
ENABLE VOUT6
I2C Data Structure (read mode) b7 Address Data 1 NOT USED b6 0 NOT USED b5 0 ZERO CROSS STATUS b4 1 P.O.D. b3 0 NOT USED b2 0 SYNC DETECT b1 0 b0 1 = Read FNC_VCR
Note) ZCD = Zero Cross Detect P.O.D. = Power on Detect
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CXA7002R
I2C Video Control TV Video Control [Data 5 Bits 0, 1, 2] Switch setting 0 xxxxx000 Vout1 Blue Encoder Blue VIN1 Bias VCR Blue VIN2 Bias Bias Encoder blue VIN1 Bias Bias Vout2 Green Encoder Green VIN3 Bias VCR Green VIN4 Bias Bias Encoder Green VIN3 Bias Bias Vout3 Red/Chroma Encoder Red VIN5 Encoder Chroma VIN6 VCR Chroma/Red VIN7 Bias Encoder Chroma VIN5 Encoder Red VIN5 Aux Chroma VIN13 Bias Vout4 CVBS/Y Encoder CVBS VIN8 Encoder Luma VIN9 Comment Digital encoder RGB or CVBS Digital encoder Y/C
1 xxxxx001
2 xxxxx010 3 xxxxx011 4 xxxxx100
VCR CVBS/Y VCR Y/C or RGB VIN10 TV CVBS VIN11 Encoder Luma VIN3 Aux CVBS VIN12 Aux CVBS/Y VIN12 Bias TV Digital encoder Y/C
5 xxxxx101
Encoder RGB and AUX CVBS
6 xxxxx110 7 xxxxx111
Aux Y/C or CVBS Video Mute
After power on all TV outputs are off (high impedance) and muted. TV RGB Gain Control [Data 5 Bits 3, 4] I2C setting "RGB GAIN" 0 xxx00xxx 1 xxx01xxx 2 xxx10xxx 3 xxx11xxx The power on default is 0dB. Extra gain/dB 0 +1 +2 +3
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CXA7002R
VCR Video Control [Data 5 Bits 5, 6, 7] Switch setting 0 000xxxxx 1 001xxxxx 2 010xxxxx 3 011xxxxx 4 100xxxxx 5 101xxxxx 6 110xxxxx 7 111xxxxx Vout5 Chroma Encoder Chroma VIN5 Encoder Chroma VIN6 VCR Chroma VIN7 Bias Encoder Chroma VIN5 Bias Aux Chroma VIN13 Bias Vout6 CVBS/Y Encoder CVBS/Y VIN8 Encoder Luma VIN9 VCR CVBS/Y VIN10 TV CVBS VIN11 Encoder Luma VIN3 Aux CVBS VIN12 Aux CVBS VIN12 Bias Comment Digital encoder Y/C Digital encoder Y/C VCR Y/C TV CVBS Encoder Y/C AUX CVBS AUX Y/C Video mute
After power on VCR outputs are off (high impedance) and muted. "Y/C MIXER CONTROL" [Data 6 Bits 0, 1] I2C setting 0 xxxxxx00 1 xxxxxx01 2 xxxxxx10 3 xxxxxx11 The power on default is no mix. Input Clamp Control "VIN3 Clamp" [Data 6 Bit 2] xxxxx0xx = GREEN input on VIN3. DC restore clamp active. (Power on default) xxxxx1xx = CVBS input on VIN3. Sync tip clamp active. Input Clamp Control "VIN7 Clamp" [Data 6 Bit 3] xxxx0xxx = CHROMA input on VIN7. Chroma bias applied. (Power on default) xxxx1xxx = RED input on VIN7. DC restore clamp applied. Input Clamp Control "VIN5 Clamp" [Data 6 Bit 4] xxx0xxxx = RED input on VIN5. DC restore clamp applied. (Power on default) xxx1xxxx = CHROMA input on VIN5. Chroma bias applied. Vout7 Mixer output No mix, Vout7 = Vout4 (CVBS) Mix Vout4 (Y) + Vout3 (C) No mix, Vout7 = Vin8 (CVBS) No mix Vout7 = Vout4 (CVBS)
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CXA7002R
Sync Select Control for RGB DC Restore Circuits "SYNC_SEL" [Data 6 Bits 5, 6] When the TV output is set to RGB + Y/CVBS mode. Then it is necessary to select the input that contains the sync information for the RGB signal. This will normally be the digital encoder CVBS or VCR CVBS input. I2C setting "SYNC_SEL" 0 x00xxxxx 1 x01xxxxx 2 x10xxxxx 3 x11xxxxx Input with sync VIN8 VIN9 VIN10 VIN12
The power on default is Vin8 ie. Digital encoder input. Video Input Gain [Data 4 Bits 6, 7] Extra gain applied to Vin1, 3, 5, 6, 8, 9 I2C setting "VIDEO INPUT GAIN" 0 00xxxxxx 1 01xxxxxx 2 10xxxxxx 3 11xxxxxx The power on default is bypass. Filter Control [Data 6 Bit 7] The filters on the six digital encoder inputs Vin1, 3, 5, 6, 8, 9 are switched on with this control bit. 0xxxxxxx = Filter bypass. Power on default. 1xxxxxxx = Filter on. Standby Mode Control [Data 7 Bits 0, 1, 2, 3, 4, 5, 6] The video outputs VOUT1, 2, 3, 4, 5, 6, 7 can be individually turned off using data byte 7. 0 = Video output off. (Power on default) 1 = Video output on. Note) When switched off, the video outputs are in a high impedance state. With a normal 150 load, the outputs will be pulled to 0V. Extra gain/dB 0 (Bypass) +1 +3 +6
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CXA7002R
Bi-directional Line Control on VCR Scart "Vout5_0V" [Data 7 Bit 7] 0xxxxxxx = Vout5 active. Connected to input specified in VCR switch table. 1xxxxxxx = Vout5 set to 0V.
I = 10mA (When set to 0V mode) 75 6dB Vout5 0V VIN_7 VOUT_5 Chroma output
VCR Scart Pin 15 Red in Chroma in Chroma out
Red in Chroma in
Fig 5. Bi-directional Line to VCR As Pin 15 on the VCR scart can be bi-directional, either chroma output or red/chroma input, it is necessary for output Vout5 to be individually controlled. When the red or chroma signal comes from the VCR, then output Vout5 is set to 0V giving the required line termination impedance of 75.
- 24 -
CXA7002R
I2C Audio Signal Control TV and Phono Audio Control [Data 2 Bits 1, 2] Switch setting 0 1 2 3 xxxxx00x xxxxx01x xxxxx10x xxxxx11x RTV, Phono_R Rin1 Rin2 Rin3 Rin4 LTV, Phono_L Lin1 Lin2 Lin3 Lin4
After power on Rin1/Lin1 are selected. VCR Audio Control [Data 2 Bits 3, 4] Switch setting 0 1 2 3 xxx00xxx xxx01xxx xxx10xxx xxx11xxx Rout1 Rin1 RTV signal Rin3 Rin4 Lout1 Lin1 LTV signal Lin3 Lin4
After power on Rin1/Lin1 are selected. TV Mono Switch [Data 2 Bit 6] Switch setting 0 1 x0xxxxxx x1xxxxxx Connection to R channel output R (R + L mix) Connection to L channel output L (R + L mix) Normal Mono mix Comment
VCR Mono Switch [Data 1 Bit 6] Switch setting 0 1 x0xxxxxx x1xxxxxx Connection to R channel output R (R + L mix) Connection to L channel output L (R + L mix) Normal Mono mix Comment
"AUDIO DISABLE" [Data 3 Bit 4] xxx0xxxx = Normal outputs xxx1xxxx = All outputs disabled. When the outputs are disabled, they are in a high impedance state. For a single supply configuration, the output voltage will drop to 0V. "PHONO BYPASS" [Data 2 Bit 0] xxxxxxx0 = Phono outputs connected after volume control block. (Default) xxxxxxx1 = Phono outputs connected before volume control block.
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CXA7002R
"TV VOL BYPASS" [Data 2 Bit 5] xx0xxxxx = TV outputs connected after volume control block. (Default) xx1xxxxx = TV outputs connected before volume control block. "MONO SWITCH" [Data 2 Bit 7] 0xxxxxxx = Mono output connected to mix of TV R + L channels. (Default) 1xxxxxxx = Mono output connected to mix of RIN1 + LIN1 inputs. "VOLUME CONTROL" [Data 1 Bits 1, 2, 3, 4, 5] Setting 0 1 2 3 4 5 6 7 8 9 10 11 31 xx00000x xx00001x xx00010x xx00011x xx00100x xx00101x xx00110x xx00111x xx01000x xx01001x xx01010x xx01011x : xx11111x Volume gain +6dB +4dB +2dB 0dB (power on default) -2dB -4dB -6dB -8dB -10dB -12dB -14dB -16dB : -56dB
"OVERLAY ENABLE" [Data 3 Bit 0] xxxxxxx0 = Overlay off (Power on default) xxxxxxx1 = Overlay on: Rin3 and Lin3 are mixed and added to Rin1, Lin1 channels. TV Mute and Zero Cross Operation When the zero cross is switched on (ZCD = 1), volume control changes are only implemented when the audio signal passes though the zero cross point. Similarly, when a mute instruction is sent, the TV outputs are only muted when the signal passes the zero cross point. This eliminates any click noise. There are two TV audio mute control bits in the bus map. By having two bits it allows the TV outputs to be muted, the TV channel changed and then un-muted all in one I2C write operation. The normal structure for a click free audio channel change is as follows: Data 1: Mute the TV audio output with the ZCD switched on. Data 2: Change the TV audio source. Data 3: Un-mute the TV audio output again with the ZCD switched on.
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CXA7002R
Operation of the Mute circuit TV Audio Mute [Data 1 Bit 0], [Data 3 Bit 7] 0 0 1 1 ZCD [Data 3 Bit 5] 0 1 0 1 Operation TV, Phono, Mono output Un-mute immediately Un-mute on next zero cross Mute immediately Mute on next zero cross
After power on TV Audio Mute = 1 and ZCD are set to 1. "TV INPUT MUTE" [Data 3 Bit 6] x0xxxxxx = The input to the TV switch is not muted. x1xxxxxx = The input to the TV switch is muted. (Power on default) "VCR INPUT MUTE" [Data 3 Bit 1] xxxxxx0x = The input to the VCR switch is not muted. xxxxxx1x = The input to the VCR switch is muted. (Power on default) "AUDIO LIMITER" [Data 1 Bit 7] When active, the output of the volume control block is limited to 2.2Vrms maximum. 0xxxxxxx = The volume control outputs are not limited. (Power on default) 1xxxxxxx = The volume control outputs are limited to 2.2Vrms.
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CXA7002R
Fast Blanking Operation (Pin 16 on SCART), FBLK The fast blanking signal instructs the TV to select either the external CVBS information or the external RGB information. This is used to superimpose an on screen display (OSD) presentation (normally RGB) upon a CVBS background. Fast blanking information has the same nominal phase as the RGB and CVBS signal, and is defined as follows, Fast blanking output at scart, 1. CVBS mode: Scart pin voltage = 0 to 0.4V 2. RGB mode: Scart pin voltage = 1 to 3.0V The threshold voltage is approximately 0.75V at the scart input. Fast Blanking I2C Control In the CXA7002R has two fast blanking inputs, one associated with the digital encoder input (FBLK_IN1) and another associated with the VCR RGB/CVBS input (FBLK_IN2). These can be selected and switched to the output using an I2C instruction. In addition, the fast blank output pin can be set to a constant 0V or +3.5V by means of the I2C control. Hence there are four possible states. These are set according to the following table. "FAST_BLANK" [Data 4 Bits 0, 1] I2C setting "BLANK_LEVEL" 0 1 2 3 xxxxxx00 xxxxxx01 xxxxxx10 xxxxxx11 Fast blank output pin voltage 0V (Power on default) Same status as Fast Blank in 1 (0/+3.5V) Same status as Fast Blank in 2 (0/+3.5V) +3.5V
Fast Blank Output Interface The Fast Blanking output pin is connected to the scart via a 75 resistor. Optional ESD protection circuitry can be added.
TV_FBLK 0V/3.5V
75
T.V. 75 Scart line 16
CXA7002R
Fig. 6. Fast Blanking Output Interface
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CXA7002R
Function Switching Operation (Pin 8 on scart) Both, VCR and TV function lines can be set to outputs and controlled independently. The TV function line has two modes, the first being control via I2C and secondly the follow mode where the output will follow the same state as the VCR input. When the VCR function lines is set as input, the level can be read back from the status resistor. An interrupt is generated when the level changes. "FNC TV_LEVEL" [Data 4 Bits 2, 3] These bits set the voltage at the output TV_FNC function line (Pin 8). I2C control "FNC_TV" 0 1 2 3 xxxx00xx xxxx01xx xxxx10xx xxxx11xx < 1V > 4.5V, < 7V > 9.5V Voltage at output Follows VCR input Internal TV External scart input 16:9 mode External scart input 4:3 mode Mode Follows VCR input
Note) After power on the output is internal TV mode ie. 0V at the pin. "FNC VCR_LEVEL" [Data 4 Bits 4, 5] These bits set the voltage at the output VCR_FNC function line (Pin 8). I2C control FNC_VCR 0 1 2 3 xx00xxxx xx01xxxx xx10xxxx xx11xxxx NA < 1V > 4.5V, < 7V > 9.5V Voltage at output Input Internal External scart input 16:9 mode External scart input 4:3 mode Mode
Note) The power on default is "Input" mode.
+12V_DIG > 4.5V, < 7V < 1V FNC_VCR 10k FNC_TV 330 maximum
> 9.5V
Inside T.V.
Scart Pin 8
Scart Pin 8
10k
Fig. 7. TV Function Switch Output
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CXA7002R
Logic and Interrupt Output Pins These two pins are open collector type and require an external pull-up resistor. Interrupt Output The interrupt pin will become a current sink for approximately 1s when the VCR input function line changes from: a) 0 to 6V, 6 to 0V b) 0 to 12V, 12 to 0V c) 6 to 12V, 12 to 6V OR When the sync detector detects that a valid video signal has been added or removed. This pin will normally be connected to +5V through a 10k resistor. Multiple interrupt signal may be generated for signals on the threshold of having a valid sync. Logic Output The logic output level can be changed using the logic output bit in the I2C register, "LOGIC_LEVEL". "LOGIC LEVEL" [Data 3 Bit 3] xxxxx0xx = Current sink mode resulting in < 0.4V saturation voltage on logic pin. (default) xxxxx1xx = Open collector/high output impedance on logic pin. Imax during current sink = 1mA
+3 to +5V External resistors 10k 10k To Micro 1s
INT LOGIC
Fig. 8. INT and Logic Line Interface
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CXA7002R
Read Mode Status Register The following information can be read from the status register: FNC VCR [Bits 0, 1] The status register bits 0, 1 hold the level of the input function line. Input pin voltage FNC_VCR 0 to +2V (default) +4.5 to +7V +9.5 to +12V SCART mode (Internal) (16:9 External) (4:3 External) Read b1 0 1 1 Data 8 b0 0 0 1
"SYNC DETECT" [Bit 2] Once a valid sync signal is detected on the input selected by "SYNC_SELECT" this bit is set to 1. The bit is reset to 0 every time the SYNC_SELECT is changed. It is assumed that when a video input is in-active then the input level will be 0V with minimum noise. "POD" (Power on Detect) [Bit 4] This bit is set to 1 after power on. It is then changed to 0 after the first I2C read. It is used to detect if the supply has been corrupted. If the POR bit is read as 1 at any time then the IC should be re-initialized to the correct I2C settings. "ZERO CROSS STATUS" [Bit 5] This audio function is used to determine if an input audio signal has passed the zero cross point.
Zero cross point Input signal
Bias voltage (2.5V)
Fig. 9. Zero Cross Point 0 = No zero cross detected. 1 = Signal has passed through zero cross point.
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CXA7002R
Description of Operation Video Section Inputs and Outputs The video section comprises of thirteen (13) high impedance inputs switched through to seven (7) video outputs. An internal +6dB amplifier is connected to each output. The amplifier is required to compensate for the 6dB attenuation that occurs at the 75 series output resistor. Outputs VOUT_1 to VOUT_7 are capable of driving 150 loads. Output VOUT_7 is designed to interface to an RF Modulator. Composite/Luminance Inputs The 4 composite (or luma) inputs are ac coupled to the input pins. The signals are first sync tip clamped to a set level. These clamps are permanently active, therefore these inputs should only be used for signals with a sync.
VCC = +5V
VCC = +5V
1Vp-p 2Vp-p 2.4V 0V Input signal 0.3V 0V Output signal
Fig. 10. CVBS/Y Waveforms RGB Inputs The RGB inputs are ac coupled to the input pins. The inputs have a dc restore circuit, which is used to set the blanking level to a fixed voltage. The clamps are controlled by the timing signal provided by the sync detect circuit. It is necessary to select the correct luma or CVBS signal associated with the RGB inputs for the sync select circuit. It is assumed that a sync signal will not be present on any of the RGB input signals. For inputs that can be either red or chroma then the clamp can be switched between the dc restore mode (for red input) and average level bias (for chroma). The RGB signals are fed through additional gain amplifiers which are controlled by I2C. These allow the nominal 0.7Vp-p signal to be increased to 0.8Vp-p, 0.9Vp-p or 1Vp-p. When the TV output is in Y/C mode, the RGB gain should be set to 0dB to prevent over amplification of the chroma output.
VCC = +5V VCC = +5V
0.7Vp-p 2.5V 0V Input signal 0.6V 0V Output signal
1.4Vp-p
Fig. 11. RGB Waveforms - 32 -
CXA7002R
Sync Detection Circuit The clamp signals, used to restore the RGB level, are generated from the sync detect circuit. By using the "SYNC_DETECT" control bits, the 4 different CVBS/Y inputs may be selected. Once selected, the signal is compared with a threshold voltage 65mV above the tip level. If the signal is less than this threshold it is not passed to the next block. If greater than the threshold, it is passed to the discrimination circuit which checks that the duty cycle is greater than 91%. The discrimination block also contains a time constant which, when a sync is detected, holds the status line high for at least 7 video lines. If a valid sync signal is detected the "SYNC_DETECT" bit in the read register is set to 1.
RGB input clamp timing
+5V_VID LOGIC Duty Discrimination
DIG CVBS/Y DIG CVBS/Y VCR CVBS/Y AUX CVBS/Y
"SYNC_SELECT" Status register "SYNC_DETECT" bit Interupt Control
68k External R/C SYNC_ID 0.1F GND_VID Comparator
Sync detect circuit
I2C
Fig. 12. Sync Detection Circuit Chroma Inputs The chroma signals are ac coupled to the input pins. The inputs have a fixed dc bias that sets the average level to approximately 3.1V for VIN_5 & VIN_7 and 2.45V for VIN_6 & VIN_13. For inputs that can also be RED signals the input circuit can be switched to the dc restore mode. Typical waveforms:
VCC = +5V VCC = +5V
2.45V or 3.1V
0.7Vp-p
1.8V 0V Chroma input pin signal 0V Chroma output pin voltage
1.4Vp-p
Fig. 13. Chroma Waveforms
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CXA7002R
Video Input Gain Stage The six inputs from the digital encoder, VIN_1, 3, 5, 6, 8, 9 may need further amplification. An adjustable gain stage is provided with settings of +1, 3, 6dB extra gain. For normal inputs (1Vp-p for CVBS, 0.7Vp-p for RGB), the gain section may be bypassed. Video Input filters To reduce any digital noise, the six inputs from the digital encode pass through a low pass filter. The filter has a high attenuation at the clock frequency of 27MHz.
0.3dB 0dB
-30dB
5MHz
27MHz
freq
Fig. 14. Basic Filter Response
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CXA7002R
Y/C Mixer A Y/C mixer can be used for mixing Luma and Chroma signals for use with an external RF modulator connected to VOUT_7. The Y/C mixer is controlled via the I2C data bus. The signal may be a mix of the TV Y/C signals or simply the TV CVBS signal. It is also possible to select the CVBS signal from the digital encoder. The circuit is shown in Fig. 15 with a trap circuit used to give 6dB attenuation at 4.43MHz of the Luma signal.
R/C 0, 1, 2 or 3dB CVBS/Y
6dB
VOUT_3
6dB Mixer switch 6dB
VOUT_4
2k VIN_8 = CVBS
VOUT_7 TRAP R
For recommended values: see application circuit.
C L
Fig. 15. Internal Y/C Mixer Circuit Switching the Video Outputs Off Each video output can be individually turned off using the I2C. When turned off, the output is set to a high impedance state and hence the current consumption and power dissipation is reduced. After power on, all the video outputs are set to the high impedance state.
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CXA7002R
Typical Video Interface Circuits Single or Dual Supply
100nF VIN_1 to VIN_13
75 Scart
Fig. 16. Video Input Interface
75 VOUT_1 to VOUT_7 75 (Line C = 400pF max.) Scart
Fig. 17. Video Output Interface
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CXA7002R
Audio Section Inputs and Outputs The audio system consists of 4 stereo inputs, 2 stereo outputs and separate mono and Phono outputs. The stereo outputs can be connected to any one of the 4 stereo inputs. All audio inputs have a -12dB attenuator except RIN_1 and LIN_1. Therefore, as an amplifier having +12dB of gain follows the interval switch, the net gain of the audio system from input to output is 0dB. The stereo input RIN_1/LIN_1 has fixed gain from input to output of +6dB. This input is typically connected to an audio DAC with full scale of 1Vrms or less. The output impedance of each audio amplifier is near zero. The output may be directly coupled to the scart for the dual supply case but must be ac coupled through a capacitor (typically 10F) for the single supply case. The outputs are capable of driving 600 loads. The user may add additional low pass filters to the outputs. TV Output Switching The TV audio section is composed of an audio switch followed by a volume control stage. The volume is adjustable from +6dB to -56dB in 2dB steps. The volume control block includes a switchable limiter function to prevent the output signals exceeding 2.2Vrms. When activated, the output signals from the volume control block will be clamped to 2.2Vrms. A mono switch that allows the mixed R + L signal to be switched to the R and L output channels follows the volume control section. TV Mute This I2C mute function acts on the TV, Phono and Mono audio circuits. Audio mute will be implemented after an audio zero cross detection to reduce click noise if "ZCD" = 1. Zero Cross Detector (ZCD) The zero cross detector reduces the effect of "click noise" when implementing a volume change or an audio mute. The volume change or mute instruction sent by I2C will only be implemented when a minimal (ie zero cross) signal amplitude is detected. It can be seen from the I2C write format that the same mute bit occurs in DATA1 and DATA3. This allows the software to action a mute, then after a delay (1/Audio_freq (min)) make any suitable changes to the audio source and then un-mute the output buffer. Such a period provides ample time to allow any audio signals to pass the zero cross point before the signal source is changed. VCR Output Switching The outputs ROUT1, LOUT1 have a fixed gain of 0dB from the input except when position 2 is selected. Position 2 selects the RTV and LTV signals. These signals are affected by the TV volume control. Phono outputs There is a stereo Phono output that carries the same signal as the TV output. This is typically used for connection to a hi-fi. The signal level of the Phono outputs is normally the same as the TV outputs however it is possible to bypass the volume section and set the Phono outputs to a fixed level. If any attenuation is required then this can be done externally.
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CXA7002R
Mono Output The mono output for the RF modulator has two settings. The first is a mix of the TV R + L channels. In this case, the output signal will have the same volume control as the RTV/LTV outputs. The second setting is a mix of the audio DAC inputs (RIN_1 + LIN_1). In this setting the output will always have fixed volume and if the tone overlay is used, this will appear on the output. Audio Overlay The inputs RIN_3, LIN_3 may be used for a normal stereo audio input or alternatively to overlay an external audio source onto the TV outputs. This may be a tone or voice. The R and L inputs are mixed and then added equally to the RIN_1 and LIN_1 inputs. The I2C control bit "AUDIO OVERLAY ENABLE" is used to switch on this facility. Audio Disable All the audio outputs may be disabled using the "Audio Output Disable" function (Data Byte 3 Bit 4). This disable mode is different from the normal mute as it puts the outputs into a high impedance state. The disable mode is different from the normal mute as it can be used for power reduction in standby modes. Hardware Mute The hardware mute input pin is used to instantaneously mute all the audio outputs. It has the same operation as the audio disable function. The outputs are muted when the pin goes below +2V.
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CXA7002R
Typical Audio Interface Circuits Supply type 1: Dual supply
0.1F RIN_1, 2, 3, 4 LIN_1, 2, 3, 4
Scart
Fig. 18. Audio Input Interface
Optional protection resistor
RTV, LTV ROUT1, LOUT1
PHONO_R, PHONO_L
Optional protection resistor
600 to 10k (Line C = 400pF max.) Scart
MONO
To RF modulator
600 to 10k (Line C = 400pF max.)
Fig. 19. Audio Output Interface Supply type 2: Single supply
0.1F RIN_1, 2, 3, 4 LIN_1, 2, 3, 4
Scart
Fig. 20. Audio Input Interface
RTV, LTV ROUT1, LOUT1
10F 600 to 10k (Line C = 400pF max.)
PHONO_R, PHONO_L 10F MONO To RF modulator
Scart
600 to 10k (Line C = 400pF max.)
For loads = 600, larger capacitors may be needed
Fig. 21. Audio Output Interface - 39 -
CXA7002R
Application in Set Top Box
Inputs B G R CVBS C Y FAST BLANKING VIN_1 VIN_3 VIN_5 VIN_8 VIN_6 VIN_9 FBLK_IN1
Outputs
Digital Encoder
VOUT_1 VOUT_2 VOUT_3 VOUT_4 TV_FBLK FNC_TV
B G T.V. R/C CVBS/Y FAST BLANKING FUNCTION SWITCH
B G VCR R/C CVBS/Y FAST BLANKING FUNCTION SWITCH
A/V switch VIN_2 VIN_4 VOUT_5 VIN_7 VOUT_6 VIN_10 FBLK_IN2 FNC_VCR
C CVBS/Y
VCR
VOUT_7 T.V. CVBS CVBS/Y C VIN_11 VIN_12 VIN_13
CVBS
RF MOD.
AUX
Fig. 22. Video Application with 6 Output Digital Encoder
Inputs B Digital G/CVBS Encoder R/C CVBS/Y FAST BLANKING Analogue C CVBS/Y Sat. B G VCR R/C CVBS/Y FAST BLANKING FUNCTION SWITCH VIN_1 VIN_3 VIN_5 VIN_8 FBLK_IN1
Outputs
VIN_6 VIN_9
VOUT_1 VOUT_2 VOUT_3 VOUT_4 TV_FBLK FNC_TV
B G T.V. R/C CVBS/Y FAST BLANKING FUNCTION SWITCH
A/V switch VIN_2 VIN_4 VOUT_5 VIN_7 VOUT_6 VIN_10 FBLK_IN2 FNC_VCR
C CVBS/Y
VCR
VOUT_7 T.V. CVBS VIN_11
CVBS
RF MOD.
AUX
CVBS/Y C
VIN12 VIN13
Fig. 23. Video Application with 4 Output Digital Encoder
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CXA7002R
Audio Application
STB Audio DAC fs = 1Vrms
RIN_1 LIN_1
RTV LTV
L
TV
R
VCR fs = 2Vrms
RIN_2 LIN_2
ROUT1 LOUT1
VCR
TV or STB Generated Voice/ Tone
RIN_3 LIN_3
PHONO_R PHONO_L
L Hi-Fi
R
AUX fs = 2Vrms
RIN_4 LIN_4
MONO
RF Modulator
TV (Mono)
Fig. 24. Audio Application
- 41 -
CXA7002R
Supply Connections
+5V (0.25V)
+12V (0.6V)
AUD_BIAS (Pin 26) AUD_BIAS (Pin 46) 22F
+5V/12V_VCCA
+12V
+5V_DIG
+5V_VID
+5V_VOUT VID_BIAS
-5V_GNDA
GND_DIG
GND_VID
GND
0.1F
-5V (0.25V)
Fig. 25. Dual Supply
+12V (0.6V)
+5V (0.25V)
22F
AUD_BIAS (Pin 26)
+5V/12V_VCCA
+12V
+5V_DIG
+5V_VID
+5V_VOUT VID_BIAS
AUD_BIAS -5V_GNDA (Pin 46) 22F
GND_DIG
GND_VID
GND
0.1F
Fig. 26. Single Ended Supply
- 42 -
Application Circuit 1 Single Supply
SUPPLIES +5V +12V
+5V 4 HEADER 100nF TV_RIN TV_LIN 68k
1 2 3 4
DIGITAL LIN1
RF MODULATOR 2 1 RF_VID
22F
DIGITAL RIN1
100nF
100nF
VCR_LIN VCR_RIN
22F
22F
VCR_ROUT
+5V
10k 100nF 100nF SCL SDA
MONO
100nF 100nF
100nF 100nF
Place Close to Supply Pins 24, 58, 64
Place Close to Supply Pins 17, 28 AUX AUDIO R
+5V
10F PHONO R
LIN _3 RIN_3 AUD_BIAS LIN_2 RIN_2 SYNC_ID LIN_1 RIN_1 INTERUPT SCL SDA GND -5V_GNDA VCC_AUD GND_AUD
AUX AUDIO L 100nF VCR_RED/C VCR_CVBS_IN VCR_GREEN VCR_BLUE 75 75 75 100nF 100nF 100nF 100nF AUX CHROMA 75 +5V 100nF
ROUT1
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
100nF
AUX CVBS 100nF 75
VOUT_2 VOUT_1 VOUT_7 TRAP VID_BIAS VIN_1 VIN_3 VIN_5 VIN_6 VIN_8 VIN_9 GND -5V_GNDA LOGIC LTV RTV
VCR_RED/C VCR_CVBS_OUT TV_CVBS_OUT TV_RED/C
75 75 75 75
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
TV_CVBS_IN 75
100nF 10F 100nF
RIN_4 LIN_4 VIN_7 VIN_10 VIN_4 VIN_2 VIN_13 VIN_12 VIN_11 +5V_VID GND_VID VOUT_5 VOUT_6 VOUT_4 VOUT_3 +5V_ VOUT
LOUT1 MONO PHONO_R PHONO_L +5V/12V_VCCA -5V_GNDA AUD_BIAS GND_DIG +5V_DIG FBLK_IN2 FNC_VCR TV_FBLK FBLK_IN1 HW_MUTE FNC_TV +12V
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
10F 10F
VCR_LOUT 10F 10F
PHONO L
+12V
22F +5V 330 75 TV_FBLANK VCR_FBLANK VCR_FNC 75
75 1 75 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TV_GREEN TV_BLUE RF_VD 75
SKT1 20 18 16 14 12 10 TV_FNC TV_LIN TV_RIN 8 6 4 2 21 19 17 15 13 11 9 7 5 3 1 TV_CVBS_OUT TV_RED/C TV_GREEN TV_BLUE TV_LOUT TV_ROUT VCR_FNC VCR_LIN VCR_RIN VCR_CVBS_IN VCR_FBLANK
SKT2 20 18 16 14 12 10 8 6 4 2 21 19 17 15 13 11 9 7 5 3 1 VCR_CVBS_OUT VCR_RED/C VCR_GREEN VCR_BLUE VCR_LOUT VCR_ROUT 100nF DIG BLUE 1 12pF 100H 2
TV_LOUT 10F TV_ROUT 10F
100nF
10k
DIG CHROMA
DIG GREEN
DIG LUMA
DIG CVBS
DIG RED/ CHROMA
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TV_CVBS_IN TV_FBLANK
330
TV_FNC +12V
75
FAST BLANKING INPUT
+5V 10k
1.8k
+5V
100nF
100nF
100nF
100nF
100nF
CXA7002R
TV SCART
VCR SCART
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Application Circuit 2 Dual Supply
+5V +12V -5V
4 HEADER
1 2 3 4
+5V 100nF TV_RIN TV_LIN 68k DIGITAL LIN1 RF MODULATOR 2 1 RF_VID DIGITAL RIN1 VCR_ROUT +5V 10k 100nF 100nF SCL SDA -5V +5V 10F PHONO R MONO ROUT1 LOUT1 MONO PHONO_R PHONO_L +5V/12V_VCCA -5V_GNDA AUD_BIAS GND_DIG +5V_DIG FBLK_IN2 FNC_VCR TV_FBLK FBLK_IN1 HW_MUTE FNC_TV +12V 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 10F 10F 10F +5V -5V VCR_LOUT 10F PHONO L +5V 330 75 TV_FBLANK
SUPPLIES
22F
Place Close to Supply Pins 24, 58, 64
Place Close to Supply Pins 17, 28
Place Close to Supply Pins 13, 27, 36 100nF 100nF 100nF 100nF 100nF 75 +5V VCR_RED/C VCR_CVBS_OUT TV_CVBS_OUT TV_RED/C 75 75 75 75 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 RIN_4 LIN_4 VIN_7 VIN_10 VIN_4 VIN_2 VIN_13 VIN_12 VIN_11 +5V_VID GND_VID VOUT_5 VOUT_6 VOUT_4 VOUT_3 +5V_ VOUT
AUX AUDIO R
AUX AUDIO L VCR_RED/C VCR_CVBS_IN VCR_GREEN VCR_BLUE 75 75 75 100nF 100nF 100nF 100nF AUX CHROMA
LIN _3 RIN_3 AUD_BIAS LIN_2 RIN_2 SYNC_ID LIN_1 RIN_1 INTERUPT SCL SDA GND -5V_GNDA VCC_AUD GND_AUD
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
100nF 100nF
VCR_LIN VCR_RIN
22F
100nF
22F
100nF
22F
100nF
VOUT_2 VOUT_1 VOUT_7 TRAP VID_BIAS VIN_1 VIN_3 VIN_5 VIN_6 VIN_8 VIN_9 GND -5V_GNDA LOGIC LTV RTV
75 1 75 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
TV_GREEN TV_BLUE RF_VD 75
SKT1 20 18 16 14 12 10 TV_FNC TV_LIN TV_RIN 8 6 4 2 21 19 17 15 13 11 9 7 5 3 1 TV_CVBS_OUT TV_RED/C TV_GREEN TV_BLUE TV_LOUT TV_ROUT VCR_FNC VCR_LIN VCR_RIN VCR_CVBS_IN VCR_FBLANK
SKT2 20 18 16 14 12 10 8 6 4 2 21 19 17 15 13 11 9 7 5 3 1 VCR_CVBS_OUT VCR_RED/C VCR_GREEN VCR_BLUE VCR_LOUT VCR_ROUT 100nF DIG BLUE 1 12pF 100H 2
-5V 100nF 10k
TV_LOUT 10F TV_ROUT 10F
DIG CHROMA
DIG GREEN
DIG LUMA
DIG CVBS
DIG RED/ CHROMA
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TV_CVBS_IN TV_FBLANK
VCR_FBLANK VCR_FNC 75
AUX CVBS 100nF 75
330
TV_FNC +12V
TV_CVBS_IN 75
100nF 10F 100nF
75
FAST BLANKING INPUT
+5V 10k
1.8k
+5V
100nF
100nF
100nF
100nF
100nF
CXA7002R
TV SCART
VCR SCART
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXA7002R
Notes on Operation 1) Supply de-coupling capacitors, 10nF and 10F in parallel should be inserted as close as possible to the supply Pins 17, 24, 28, 35, 58 and 64. When using the dual supply configuration apply the capacitors to Pins 13, 27, 36 in addition to the listed supply pins. 2) To minimize crosstalk, attention should be given to the routing of audio and video to the IC inputs. PCB track lengths should be kept as short as possible and preferably, audio placed on a separate layer to the video. 3) Attention should be given to the electrolytic capacitors on the output pins. In single supply configuration the audio pin dc bias voltage will be approximately 6.0V, therefore the positive terminal of the capacitors should be orientated towards the device pin. 4) To minimize stray capacitance the 75 series resistor on video outputs VOUT_1 to VOUT_7 should be mounted as close as possible to the device Pins 1, 2, 3, 60, 61, 62 and 63. 5) Pins 10, 11, 46, 52, 56, 57 have reduced ESD performance and external protection circuitry may be added. As shown in the application schematic, zener diodes may be added. Zener diodes with a rating > 5V may be used.
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CXA7002R
Typical Performance Curves
Video gain - VOUT_1, 2, 3, 4, 5, 6
7 6 5 4 3 2 1 0 1 10 Frequency [MHz] VOUT_1, 2, 3 VOUT_4, 5, 6
Gain [dB]
100
Video gain - VOUT_7
7 6 5 4 3 2 1 0 -1 -2 1
Mixer Off Mixer On
Gain [dB]
10 Frequency [MHz]
100
Audio gain
1 0
Gain [dB]
-1 -2 -3 -4 1 10 100 Frequency [kHz] 1000 10000
Audio THD + N RIN_1/LIN_1 to TV outputs
-20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90
Audio THD + N RIN_2, 3, 4/LIN2, 3, 4 to TV outputs
dB
0.1
0.3
0.5
0.70.8
1 1.11.2
1.41.5
dB
0.2
0.6
1 1.2
1.6
2 2.2 2.4
2.8 3
Input level [Vrms]
Input level [Vrms]
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CXA7002R
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
12.0 0.2 48 49 10.0 0.1 33 32
(11.0)
A 64 1 0.5 b 16 0.13 M + 0.2 1.5 - 0.1 17 (0.22)
0.5 0.2
0.1
0.1 0.1 b = 0.18 0.03
0.125 0.04
0 to 10
0.5 0.2
DETAIL B: PALLADIUM DETAIL A NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L01 P-LQFP64-10x10-0.5 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.3g
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Sony Corporation

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